The present invention relates to a semiconductor chip packaging technology, and more particularly to a wafer level package having a side package.
Semiconductor chip packages provide input and output connections to a semiconductor chip for an external device, as well as physical protection for the semiconductor chip. The wafer level package is one type of semiconductor chip package. The wafer level package is a package formed on a semiconductor wafer, rather than on a die (a “die” refers to a semiconductor chip that has been separated from the wafer). Forming a wafer level package on a wafer has the advantages of providing more complete integration of the package functions and the semiconductor chip functions, improving the thermal and electrical characteristics of the semiconductor chips, and decreasing the size of the semiconductor chip package. Additionally, since the wafer level package is formed in a single process, the price to manufacture the semiconductor chip is reduced.
However, drawbacks do exist with wafer level packaging. Most notably, the inability of the process to package all sides of the semiconductor chip. For example, with wafer level packaging, sides of individual dies are left unpackaged. A semiconductor chip not having a package body surrounding all sides of the semiconductor chip is vulnerable to physical damage, for example, from physical contact with objects of the surrounding environment during the manufacturing process, or from the handling of the semiconductor chip. Of particular concern is the damage an exposed semiconductor chip may receive during the process for wafer back lapping, which is performed to decrease the thickness of the semiconductor chip.